Systematic-error signals in the AC josephson voltage standard: measurement and reduction

Abstract

We investigate the dominant frequency-dependent systematic-error signals (SESs) in the AC Josephson voltage standard. We describe our error measurement technique and a number of methods to reduce the errors. Most importantly, we found that a small change in on-chip wiring significantly reduces the SES, improves SES measurement stability, and enables a suitable bias correction method. We show that direct analog-to-digital converter measurements of the SES of two on-chip Josephson arrays are in very good agreement with errors inferred from AC-DC transfer standard measurements. Finally, we demonstrate that the reduction of the SES using these techniques greatly improves the agreement between the AC-DC differences of the two arrays as well as the absolute AC voltage accuracy.